Electronic devices of various types are often coupled in series with like devices (also referred to as being “cascaded” or “daisy-chained”) in order to meet application requirements without requiring multiple connections to a common controller. For example, serial data devices are often coupled in series to avoid the need for a common microcontroller or microprocessor to individually address each device. In this type of an arrangement, the serial data output of one device is coupled to the serial data input of the next successive device. Illustrative devices of this type include drivers, such as display drivers, which are often cascaded in order to drive a number of display devices or device segments without requiring multiple microprocessor connections.
In such configurations, a common clock signal is typically used to ensure that the data shifted from one device to the next will remain synchronous, thereby ensuring data integrity. However, having large numbers of devices sharing the common clock signal is undesirable in some types of systems. For example in some systems, the devices receiving data may be located remotely from the controlling device and each other, connected with the use of a daisy-chained wiring harness. In such systems, the loading on the common clock line, due to the large number of controlled devices, results in greatly increased drive requirements for the clock signal. Furthermore, the long length of the daisy-chained clock signal line can lead to noise and clock signal reflections that, without the use of more expensive wiring or reduced data rates and filtering, may degrade the noise margin and thus, the data integrity of the system.
To avoid the aforementioned problems, the clock signal entering each controlled device may be buffered and used to drive the clock input of the next controlled device in the serial daisy chain. The buffered clock resolves the aforementioned issues since the clock output signal of each device need only drive the next device in the chain.
However, the buffered clock system can give rise to other issues when the length of the daisy-chain is very long and the data rate desired is high relative to the speed of the controlling system. In such a system, each time the clock signal passes through a controlled device, the logic high portion of the clock signal will be shortened or lengthened due to the nature of the buffer circuitry, thereby causing clock signal skewing and delays that can compromise data integrity. Furthermore, as the clock signal is buffered from one device to the next, the reductions/increases are cumulative and can result in the high or low state of the clock signal disappearing entirely (referred to herein as clock loss) and the total loss of all data for subsequent devices in the daisy chain.
In practice this occurs more commonly than might be expected due to differences in the P channel and N channel MOSFET devices that produce the composite threshold voltage of a standard CMOS logic buffer. For example, even if a buffer is designed to have a nominal half supply voltage threshold and nominally equal falling and rising propagation delays, in a given wafer fabrication lot, due to normal process variation, when the N channel threshold is high and the P channel threshold is low (less negative), the composite threshold of the buffer will be higher than the nominal half supply. In this case, because the incoming clock signal has a finite rising and falling time, the logic high portion of the buffered clock signal will be reduced as compared to the incoming clock signal. Furthermore because all devices in the wafer fabrication lot are likely to be similar, the reduction/increase in the duration of the logic high state will be systematic and can easily result in the total loss of the clock signal when many devices are daisy-chained.
Another issue associated with cascading serial data devices involves ensuring that the output data from one device is clocked into the successive device before a next clock event at the first device causes the output data to be updated. The amount of time necessary for data to be held at the input to a device after the clock edge triggered event to ensure that it will be correctly clocked into the device can be referred to as the “hold time” and the amount of time preceding a clock edge triggered event that data needs to be present at the device input for accurate clocking can be referred to as the “setup time.” In one example, output data from a device N is clocked into the successive device N+1 at the moment of a rising edge of the clock signal and this is also the time when new data in the device N begins to transfer to its output. Ideally, propagation delays allow the old data to be clocked into the N+1 device before the new data arrives at the output of the N device.
Some designs simply rely on propagation delays through the serial data output buffer to hold the data long enough for it to be clocked into the next device before the new data arrives at the serial data output. However, this sequence of events cannot be ensured with certainty, particularly given process and temperature variations, thereby risking interference with the correct transfer of data.
One technique for avoiding this race condition is to use synchronous logic that is clocked off another asynchronous clock signal to ensure that no capacitive/delay holding is required. In such cases the data resynchronization may be achieved through the use of other logic circuits. However, such designs have the disadvantage that due to the asynchronous nature of the other clock, the logic and thus the data rate is required to run at a slower speed to ensure that correct operation is maintained.